/****************************************************************************
 *
 * Copyright 2017 Samsung Electronics All Rights Reserved.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing,
 * software distributed under the License is distributed on an
 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
 * either express or implied. See the License for the specific
 * language governing permissions and limitations under the License.
 *
 ****************************************************************************/
/****************************************************************************
 * os/arch/arm/src/s5j/chip/s5j_uart.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/

#ifndef __ARCH_ARM_SRC_S5J_CHIP_S5JT200_UART_H
#define __ARCH_ARM_SRC_S5J_CHIP_S5JT200_UART_H

/****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/

/* Register Address *********************************************************/
#define S5J_UART_BASE(n) \
		((n) == 4 ? S5J_UART4_BASE : (S5J_UART0_BASE + 0x10000 * (n)))

#define S5J_UART_ULCON_OFFSET		0x0000
#define S5J_UART_UCON_OFFSET		0x0004
#define S5J_UART_UFCON_OFFSET		0x0008
#define S5J_UART_UMCON_OFFSET		0x000c
#define S5J_UART_UTRSTAT_OFFSET		0x0010
#define S5J_UART_UERSTAT_OFFSET		0x0014
#define S5J_UART_UFSTAT_OFFSET		0x0018
#define S5J_UART_UMSTAT_OFFSET		0x001c
#define S5J_UART_UTXH_OFFSET		0x0020
#define S5J_UART_URXH_OFFSET		0x0024
#define S5J_UART_UBRDIV_OFFSET		0x0028
#define S5J_UART_UFRACVAL_OFFSET	0x002c
#define S5J_UART_UINTP_OFFSET		0x0030
#define S5J_UART_UINTS_OFFSET		0x0034
#define S5J_UART_UINTM_OFFSET		0x0038

#define S5J_UART_ULCON(n)			(S5J_UART_BASE(n) + S5J_UART_ULCON_OFFSET)
#define S5J_UART_UCON(n)			(S5J_UART_BASE(n) + S5J_UART_UCON_OFFSET)
#define S5J_UART_UFCON(n)			(S5J_UART_BASE(n) + S5J_UART_UFCON_OFFSET)
#define S5J_UART_UMCON(n)			(S5J_UART_BASE(n) + S5J_UART_UMCON_OFFSET)
#define S5J_UART_UTRSTAT(n)			(S5J_UART_BASE(n) + S5J_UART_UTRSTAT_OFFSET)
#define S5J_UART_UERSTAT(n)			(S5J_UART_BASE(n) + S5J_UART_UERSTAT_OFFSET)
#define S5J_UART_UFSTAT(n)			(S5J_UART_BASE(n) + S5J_UART_UFSTAT_OFFSET)
#define S5J_UART_UMSTAT(n)			(S5J_UART_BASE(n) + S5J_UART_UMSTAT_OFFSET)
#define S5J_UART_UTXH(n)			(S5J_UART_BASE(n) + S5J_UART_UTXH_OFFSET)
#define S5J_UART_URXH(n)			(S5J_UART_BASE(n) + S5J_UART_URXH_OFFSET)
#define S5J_UART_UBRDIV(n)			(S5J_UART_BASE(n) + S5J_UART_UBRDIV_OFFSET)
#define S5J_UART_UFRACVAL(n)		(S5J_UART_BASE(n) + S5J_UART_UFRACVAL_OFFSET)
#define S5J_UART_UINTP(n)			(S5J_UART_BASE(n) + S5J_UART_UINTP_OFFSET)
#define S5J_UART_UINTS(n)			(S5J_UART_BASE(n) + S5J_UART_UINTS_OFFSET)
#define S5J_UART_UINTM(n)			(S5J_UART_BASE(n) + S5J_UART_UINTM_OFFSET)

/* Line Control register ****************************************************/
#define UART_ULCON_SAMPLING_SHIFT		7
#define UART_ULCON_SAMPLING_MASK		(0x1 << UART_ULCON_SAMPLING_SHIFT)
#define UART_ULCON_SAMPLING_16			(0x0 << UART_ULCON_SAMPLING_SHIFT)
#define UART_ULCON_SAMPLING_8			(0x1 << UART_ULCON_SAMPLING_SHIFT)

#define UART_ULCON_INFRARED_SHIFT		6
#define UART_ULCON_INFRARED_MASK		(0x1 << UART_ULCON_INFRARED_SHIFT)
#define UART_ULCON_INFRARED_NORMAL		(0x0 << UART_ULCON_INFRARED_SHIFT)
#define UART_ULCON_INFRARED_IRTXRX		(0x1 << UART_ULCON_INFRARED_SHIFT)

#define UART_ULCON_PARITY_SHIFT			5
#define UART_ULCON_PARITY_MASK			(0x7 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_NONE			(0x0 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_ODD			(0x4 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_EVEN			(0x5 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_FORCE1		(0x6 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_FORCE0		(0x7 << UART_ULCON_PARITY_SHIFT)

#define UART_ULCON_STOPBITS_SHIFT		2
#define UART_ULCON_STOPBITS_MASK		(0x1 << UART_ULCON_STOPBITS_SHIFT)
#define UART_ULCON_STOPBITS_1BIT		(0x0 << UART_ULCON_STOPBITS_SHIFT)
#define UART_ULCON_STOPBITS_2BITS		(0x1 << UART_ULCON_STOPBITS_SHIFT)

#define UART_ULCON_DATABITS_SHIFT		0
#define UART_ULCON_DATABITS_MASK		(0x3 << UART_ULCON_DATABITS_SHIFT)
#define UART_ULCON_DATABITS_5BITS		(0x0 << UART_ULCON_DATABITS_SHIFT)
#define UART_ULCON_DATABITS_6BITS		(0x1 << UART_ULCON_DATABITS_SHIFT)
#define UART_ULCON_DATABITS_7BITS		(0x2 << UART_ULCON_DATABITS_SHIFT)
#define UART_ULCON_DATABITS_8BITS		(0x3 << UART_ULCON_DATABITS_SHIFT)

/* Control register *********************************************************/
#define UART_UCON_TX_DMA_BURST_SHIFT	20
#define UART_UCON_TX_DMA_BURST_MASK		(0x7 << UART_UCON_TX_DMA_BURST_SHIFT)
#define UART_UCON_TX_DMA_BURST_1BYTE	(0x0 << UART_UCON_TX_DMA_BURST_SHIFT)
#define UART_UCON_TX_DMA_BURST_4BYTES	(0x1 << UART_UCON_TX_DMA_BURST_SHIFT)
#define UART_UCON_TX_DMA_BURST_8BYTES	(0x2 << UART_UCON_TX_DMA_BURST_SHIFT)

#define UART_UCON_RX_DMA_BURST_SHIFT	16
#define UART_UCON_RX_DMA_BURST_MASK		(0x7 << UART_UCON_RX_DMA_BURST_SHIFT)
#define UART_UCON_RX_DMA_BURST_1BYTE	(0x0 << UART_UCON_RX_DMA_BURST_SHIFT)
#define UART_UCON_RX_DMA_BURST_4BYTES	(0x1 << UART_UCON_RX_DMA_BURST_SHIFT)
#define UART_UCON_RX_DMA_BURST_8BYTES	(0x2 << UART_UCON_RX_DMA_BURST_SHIFT)
#define UART_UCON_RX_DMA_BURST_16BYTES	(0x3 << UART_UCON_RX_DMA_BURST_SHIFT)

#define UART_UCON_RX_TOUT_SHIFT			12
#define UART_UCON_RX_TOUT_MASK			(0x7 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_8FRAMES		(0x0 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_16FRAMES		(0x1 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_24FRAMES		(0x2 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_32FRAMES		(0x3 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_40FRAMES		(0x4 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_48FRAMES		(0x5 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_56FRAMES		(0x6 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_64FRAMES		(0x7 << UART_UCON_RX_TOUT_SHIFT)

#define UART_UCON_RX_FIFO_EMPTY_SHIFT	11
#define UART_UCON_RX_FIFO_EMPTY_MASK	(0x1 << UART_UCON_RX_FIFO_EMPTY_SHIFT)
#define UART_UCON_RX_FIFO_EMPTY_DISABLE	(0x0 << UART_UCON_RX_FIFO_EMPTY_SHIFT)
#define UART_UCON_RX_FIFO_EMPTY_ENABLE	(0x1 << UART_UCON_RX_FIFO_EMPTY_SHIFT)

#define UART_UCON_RX_TOUT_DMAS_SHIFT	10
#define UART_UCON_RX_TOUT_DMAS_MASK		(0x1 << UART_UCON_RX_TOUT_DMAS_SHIFT)
#define UART_UCON_RX_TOUT_DMAS_DISABLE	(0x0 << UART_UCON_RX_TOUT_DMAS_SHIFT)
#define UART_UCON_RX_TOUT_DMAS_ENABLE	(0x1 << UART_UCON_RX_TOUT_DMAS_SHIFT)

#define UART_UCON_TX_INTTYPE_SHIFT		9
#define UART_UCON_TX_INTTYPE_MASK		(UART_UCON_TX_INTTYPE_SHIFT)
#define UART_UCON_TX_INTTYPE_PULSE		(0x0 << UART_UCON_TX_INTTYPE_SHIFT)
#define UART_UCON_TX_INTTYPE_LEVEL		(0x1 << UART_UCON_TX_INTTYPE_SHIFT)

#define UART_UCON_RX_INTTYPE_SHIFT		8
#define UART_UCON_RX_INTTYPE_MASK		(UART_UCON_RX_INTTYPE_SHIFT)
#define UART_UCON_RX_INTTYPE_PULSE		(0x0 << UART_UCON_RX_INTTYPE_SHIFT)
#define UART_UCON_RX_INTTYPE_LEVEL		(0x1 << UART_UCON_RX_INTTYPE_SHIFT)

#define UART_UCON_RX_TOUTINT_SHIFT		7
#define UART_UCON_RX_TOUTINT_MASK		(0x1 << UART_UCON_RX_TOUTINT_SHIFT)
#define UART_UCON_RX_TOUTINT_DISABLE	(0x0 << UART_UCON_RX_TOUTINT_SHIFT)
#define UART_UCON_RX_TOUTINT_ENABLE		(0x1 << UART_UCON_RX_TOUTINT_SHIFT)

#define UART_UCON_RX_ERRINT_SHIFT		6
#define UART_UCON_RX_ERRINT_MASK		(0x1 << UART_UCON_RX_ERRINT_SHIFT)
#define UART_UCON_RX_ERRINT_DISABLE		(0x0 << UART_UCON_RX_ERRINT_SHIFT)
#define UART_UCON_RX_ERRINT_ENABLE		(0x1 << UART_UCON_RX_ERRINT_SHIFT)

#define UART_UCON_LOOPBACK_SHIFT		5
#define UART_UCON_LOOPBACK_MASK			(0x1 << UART_UCON_LOOPBACK_SHIFT)
#define UART_UCON_LOOPBACK_DISABLE		(0x0 << UART_UCON_LOOPBACK_SHIFT)
#define UART_UCON_LOOPBACK_ENABLE		(0x1 << UART_UCON_LOOPBACK_SHIFT)

#define UART_UCON_SEND_BREAK_SHIFT		4
#define UART_UCON_SEND_BREAK			(0x1 << UART_UCON_SEND_BREAK_SHIFT)

#define UART_UCON_TX_MODE_SHIFT			2
#define UART_UCON_TX_MODE_MASK			(0x3 << UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_TX_MODE_DISABLE		(0x0 << UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_TX_MODE_IRQPOLL		(0x1 << UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_TX_MODE_DMA			(0x2 << UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_TX_MODE_RESERVED		(0x3 << UART_UCON_TX_MODE_SHIFT)

#define UART_UCON_RX_MODE_SHIFT			0
#define UART_UCON_RX_MODE_MASK			(0x3 << UART_UCON_RX_MODE_SHIFT)
#define UART_UCON_RX_MODE_DISABLE		(0x0 << UART_UCON_RX_MODE_SHIFT)
#define UART_UCON_RX_MODE_IRQPOLL		(0x1 << UART_UCON_RX_MODE_SHIFT)
#define UART_UCON_RX_MODE_DMA			(0x2 << UART_UCON_RX_MODE_SHIFT)
#define UART_UCON_RX_MODE_RESERVED		(0x3 << UART_UCON_RX_MODE_SHIFT)

/* FIFO Control register ****************************************************/
#define UART_UFCON_TX_FIFO_TRIG_SHIFT	8
#define UART_UFCON_TX_FIFO_TRIG_MASK	(0x7 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_0BYTE	(0x0 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_2BYTES	(0x1 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_4BYTES	(0x2 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_6BYTES	(0x3 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_8BYTES	(0x4 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_10BYTES	(0x4 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_12BYTES	(0x5 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_14BYTES	(0x6 << UART_UFCON_TX_FIFO_TRIG_SHIFT)

#define UART_UFCON_RX_FIFO_TRIG_SHIFT	4
#define UART_UFCON_RX_FIFO_TRIG_MASK	(0x7 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_0BYTE	(0x0 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_2BYTES	(0x1 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_4BYTES	(0x2 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_6BYTES	(0x3 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_8BYTES	(0x4 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_10BYTES	(0x4 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_12BYTES	(0x5 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_14BYTES	(0x6 << UART_UFCON_RX_FIFO_TRIG_SHIFT)

#define UART_UFCON_TX_FIFO_RESET_SHIFT	2
#define UART_UFCON_TX_FIFO_RESET		(0x1 << UART_UFCON_TX_FIFO_RESET_SHIFT)

#define UART_UFCON_RX_FIFO_RESET_SHIFT	1
#define UART_UFCON_RX_FIFO_RESET		(0x1 << UART_UFCON_RX_FIFO_RESET_SHIFT)

#define UART_UFCON_FIFO_SHIFT			0
#define UART_UFCON_FIFO_MASK			(0x1 << UART_UFCON_FIFO_SHIFT)
#define UART_UFCON_FIFO_DISABLE			(0x0 << UART_UFCON_FIFO_SHIFT)
#define UART_UFCON_FIFO_ENABLE			(0x1 << UART_UFCON_FIFO_SHIFT)

/* Modem Control register ***************************************************/
#define UART_UMCON_RTS_TRIG_SHIFT		5
#define UART_UMCON_RTS_TRIG_MASK		(0x7 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_15BYTES		(0x0 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_14BYTES		(0x1 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_12BYTES		(0x2 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_10BYTES		(0x3 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_8BYTES		(0x4 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_6BYTES		(0x5 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_4BYTES		(0x6 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_2BYTES		(0x7 << UART_UMCON_RTS_TRIG_SHIFT)

#define UART_UMCON_AFC_SHIFT			4
#define UART_UMCON_AFC_MASK				(0x1 << UART_UMCON_AFC_SHIFT)
#define UART_UMCON_AFC_DISABLE			(0x0 << UART_UMCON_AFC_SHIFT)
#define UART_UMCON_AFC_ENABLE			(0x0 << UART_UMCON_AFC_SHIFT)

#define UART_UMCON_MODEM_INT_SHIFT		3
#define UART_UMCON_MODEM_INT_MASK		(0x1 << UART_UMCON_MODEM_INT_SHIFT)
#define UART_UMCON_MODEM_INT_DISABLE	(0x0 << UART_UMCON_MODEM_INT_SHIFT)
#define UART_UMCON_MODEM_INT_ENABLE		(0x1 << UART_UMCON_MODEM_INT_SHIFT)

#define UART_UMCON_REQ_TO_SEND_SHIFT	0
#define UART_UMCON_REQ_TO_SEND_MASK		(0x1 << UART_UMCON_REQ_TO_SEND_SHIFT)
#define UART_UMCON_REQ_TO_SEND_HIGH		(0x0 << UART_UMCON_REQ_TO_SEND_SHIFT)
#define UART_UMCON_REQ_TO_SEND_LOW		(0x1 << UART_UMCON_REQ_TO_SEND_SHIFT)

/* Tx/Rx Status register ****************************************************/
#define UART_UTRSTAT_RX_FIFO_CNT_SHIFT	16
#define UART_UTRSTAT_RX_FIFO_CNT_MASK	(0xff << UART_UTRSTAT_RXFIFO_CNT_SHIFT)

#define UART_UTRSTAT_TX_DMA_SHIFT		12
#define UART_UTRSTAT_TX_DMA_MASK		(0xf << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_IDLE		(0x0 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_BURST_REQ	(0x1 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_BURST_ACK	(0x2 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_BURST_NEXT	(0x3 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_SINGLE_REQ	(0x4 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_SINGLE_ACK	(0x5 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_SINGLE_NEXT	(0x6 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_LBURST_REQ	(0x7 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_LBURST_ACK	(0x8 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_LSINGLE_REQ	(0x9 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_LSINGLE_ACK	(0xa << UART_UTRSTAT_TX_DMA_SHIFT)

#define UART_UTRSTAT_RX_DMA_SHIFT		8
#define UART_UTRSTAT_RX_DMA_MASK		(0xf << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_IDLE		(0x0 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_BURST_REQ	(0x1 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_BURST_ACK	(0x2 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_BURST_NEXT	(0x3 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_SINGLE_REQ	(0x4 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_SINGLE_ACK	(0x5 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_SINGLE_NEXT	(0x6 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_LBURST_REQ	(0x7 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_LBURST_ACK	(0x8 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_LSINGLE_REQ	(0x9 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_LSINGLE_ACK	(0xa << UART_UTRSTAT_RX_DMA_SHIFT)

#define UART_UTRSTAT_RX_TOUT_SHIFT		3
#define UART_UTRSTAT_RX_TOUT_MASK		(0x1 << UART_UTRSTAT_RX_TOUT_SHIFT)
#define UART_UTRSTAT_RX_TOUT_NONE		(0x0 << UART_UTRSTAT_RX_TOUT_SHIFT)
#define UART_UTRSTAT_RX_TOUT_TIMEOUT	(0x1 << UART_UTRSTAT_RX_TOUT_SHIFT)

#define UART_UTRSTAT_TX_SHIFT			2
#define UART_UTRSTAT_TX_MASK			(0x1 << UART_UTRSTAT_TX_SHIFT)
#define UART_UTRSTAT_TX_NOT_EMPTY		(0x0 << UART_UTRSTAT_TX_SHIFT)
#define UART_UTRSTAT_TX_EMPTY			(0x1 << UART_UTRSTAT_TX_SHIFT)

#define UART_UTRSTAT_TX_BUF_SHIFT		1
#define UART_UTRSTAT_TX_BUF_MASK		(0x1 << UART_UTRSTAT_TX_BUF_SHIFT)
#define UART_UTRSTAT_TX_BUF_NOT_EMPTY	(0x0 << UART_UTRSTAT_TX_BUF_SHIFT)
#define UART_UTRSTAT_TX_BUF_EMPTY		(0x1 << UART_UTRSTAT_TX_BUF_SHIFT)

#define UART_UTRSTAT_RX_BUF_SHIFT		0
#define UART_UTRSTAT_RX_BUF_MASK		(0x1 << UART_UTRSTAT_RX_BUF_SHIFT)
#define UART_UTRSTAT_RX_BUF_NOT_EMPTY	(0x0 << UART_UTRSTAT_RX_BUF_SHIFT)
#define UART_UTRSTAT_RX_BUF_EMPTY		(0x1 << UART_UTRSTAT_RX_BUF_SHIFT)

/* Rx Error Status register *************************************************/
#define UART_UERSTAT_BREAK_DETECT		0x8
#define UART_UERSTAT_FRAME_ERROR		0x4
#define UART_UERSTAT_PARITY_ERROR		0x2
#define UART_UERSTAT_OVERRUN_ERROR		0x1

/* FIFO status register *****************************************************/
#define UART_UFSTAT_TX_FIFO_FULL_SHIFT	24
#define UART_UFSTAT_TX_FIFO_FULL_MASK	(0x1 << UART_UFSTAT_TX_FIFO_FULL_SHIFT)
#define UART_UFSTAT_TX_FIFO_FULL		(0x1 << UART_UFSTAT_TX_FIFO_FULL_SHIFT)

#define UART_UFSTAT_TX_FIFO_COUNT_SHIFT	16
#define UART_UFSTAT_TX_FIFO_COUNT_MASK	(0xff << UART_UFSTAT_TX_FIFO_COUNT_SHIFT)

#define UART_UFSTAT_RX_FIFO_ERROR_SHIFT	9
#define UART_UFSTAT_RX_FIFO_ERROR_MASK	(0x1 << UART_UFSTAT_RX_FIFO_ERROR_SHIFT)
#define UART_UFSTAT_RX_FIFO_ERROR		(0x1 << UART_UFSTAT_RX_FIFO_ERROR_SHIFT)

#define UART_UFSTAT_RX_FIFO_FULL_SHIFT	8
#define UART_UFSTAT_RX_FIFO_FULL_MASK	(0x1 << UART_UFSTAT_RX_FIFO_FULL_SHIFT)
#define UART_UFSTAT_RX_FIFO_FULL		(0x1 << UART_UFSTAT_RX_FIFO_FULL_SHIFT)

#define UART_UFSTAT_RX_FIFO_COUNT_SHIFT	0
#define UART_UFSTAT_RX_FIFO_COUNT_MASK	(0xff << UART_UFSTAT_RX_FIFO_COUNT_SHIFT)

/* Modem Status register ****************************************************/
#define UART_UMSTAT_DELTA_CTS_SHIFT		4
#define UART_UMSTAT_DELTA_CTS_MASK		(0x1 << UART_UMSTAT_DELTA_CTS_SHIFT)
#define UART_UMSTAT_DELTA_CTS_NOCHANGE	(0x0 << UART_UMSTAT_DELTA_CTS_SHIFT)
#define UART_UMSTAT_DELTA_CTS_CHANGED	(0x1 << UART_UMSTAT_DELTA_CTS_SHIFT)

#define UART_UMSTAT_NCTS_SHIFT			0
#define UART_UMSTAT_NCTS_MASK			(0x1 << UART_UMSTAT_NCTS_SHIFT)
#define UART_UMSTAT_NCTS_HIGH			(0x0 << UART_UMSTAT_NCTS_SHIFT)
#define UART_UMSTAT_NCTS_LOW			(0x1 << UART_UMSTAT_NCTS_SHIFT)

/* INterrupt Pending register ***********************************************/
#define UART_UINTP_MODEM_SHIFT			3
#define UART_UINTP_MODEM_MASK			(0x1 << UART_UINTP_MODEM_SHIFT)
#define UART_UINTP_MODEM				(0x1 << UART_UINTP_MODEM_SHIFT)

#define UART_UINTP_TXD_SHIFT			2
#define UART_UINTP_TXD_MASK				(0x1 << UART_UINTP_TXD_SHIFT)
#define UART_UINTP_TXD					(0x1 << UART_UINTP_TXD_SHIFT)

#define UART_UINTP_ERROR_SHIFT			1
#define UART_UINTP_ERROR_MASK			(0x1 << UART_UINTP_ERROR_SHIFT)
#define UART_UINTP_ERROR				(0x1 << UART_UINTP_ERROR_SHIFT)

#define UART_UINTP_RXD_SHIFT			0
#define UART_UINTP_RXD_MASK				(0x1 << UART_UINTP_RXD_SHIFT)
#define UART_UINTP_RXD					(0x1 << UART_UINTP_RXD_SHIFT)

/* Interrupt Source register ************************************************/
#define UART_UINTS_MODEM_SHIFT			3
#define UART_UINTS_MODEM_MASK			(0x1 << UART_UINTS_MODEM_SHIFT)
#define UART_UINTS_MODEM				(0x1 << UART_UINTS_MODEM_SHIFT)

#define UART_UINTS_TXD_SHIFT			2
#define UART_UINTS_TXD_MASK				(0x1 << UART_UINTS_TXD_SHIFT)
#define UART_UINTS_TXD					(0x1 << UART_UINTS_TXD_SHIFT)

#define UART_UINTS_ERROR_SHIFT			1
#define UART_UINTS_ERROR_MASK			(0x1 << UART_UINTS_ERROR_SHIFT)
#define UART_UINTS_ERROR				(0x1 << UART_UINTS_ERROR_SHIFT)

#define UART_UINTS_RXD_SHIFT			0
#define UART_UINTS_RXD_MASK				(0x1 << UART_UINTS_RXD_SHIFT)
#define UART_UINTS_RXD					(0x1 << UART_UINTS_RXD_SHIFT)

/* Interrupt Mask register **************************************************/
#define UART_UINTM_MODEM_SHIFT			3
#define UART_UINTM_MODEM_MASK			(0x1 << UART_UINTM_MODEM_SHIFT)

#define UART_UINTM_TXD_SHIFT			2
#define UART_UINTM_TXD_MASK				(0x1 << UART_UINTM_TXD_SHIFT)

#define UART_UINTM_ERROR_SHIFT			1
#define UART_UINTM_ERROR_MASK			(0x1 << UART_UINTM_ERROR_SHIFT)

#define UART_UINTM_RXD_SHIFT			0
#define UART_UINTM_RXD_MASK				(0x1 << UART_UINTM_RXD_SHIFT)

#endif /* __ARCH_ARM_SRC_S5J_CHIP_S5JT200_UART_H */
